1. Field of the Invention
The present invention relates to a bonding pad structure of a semiconductor device, and more particularly to a bonding pad structure of a semiconductor device having improved bondability.
2. Description of the Related Art
As electrical components are made smaller, various strategies have been adopted to reduce the amount of space devoted to connections between the chip containing the integrated circuit devices and the printed circuit board on which the chips are mounted. Electrical connections between integrated circuits on a chip and the printed circuit board are made through bonding pads typically provided at the periphery of the chip. Conventional bonding pad structures may include a bonding metal layer and a barrier metal layer deposited over an underlying dielectric layer such as a silicon oxide layer. The bonding metal layer is in electrical contact with one or more semiconductor devices in the chip. The barrier metal layer on the underlying dielectric layer helps adhere the bonding metal layer, typically aluminum, to the underlying dielectric layer. The bonding metal layers of the conventional bonding pad structures have been observed to delaminate or have layers that separate from one another in response to external forces like those applied in wire bonding processes of the type typically used attaching wires to the bonding pads.
Connections between the bonding pads of a chip and the leads printed on the circuit board have conventionally been provided through the lead frame used as part of lead frame packaging methods. In such lead frame packaging methods, the chip is mounted to a frame which incorporates an array of electrical leads, with thin bonding wires connecting the bonding pads to the electrical leads on the lead frame. The entire chip and lead frame assembly is encapsulated in plastic and then mounted on the printed circuit board through the leads extending from the package. Another packaging method which is called the chip-on-board method, and the semiconductor chip is mounted directly to the printed circuit board, have significant space and weight advantages over conventional lead frame packaging methods. Electrical connections between the bonding pads of the chip and the circuit board on which the chip is mounted are typically provided by wire bonding thin wires between the chips bonding pads and the leads printed on the board. The wire bonds may be formed using a variety of techniques including ultrasonic bonding and thermocompression bonding. Ultrasonic bonding uses ultrasonic waves or vibration to attach the wire to the bonding pad. Thermocompression bonding uses a combination of elevated temperature and compressive force to attach the wire to the bonding pad. Both of these bonding techniques impart mechanical and/or thermal energy directly to the bonding pad area and so can damage the bonding pad and the chip. Proper control of the process variables used in these techniques, such as bonding temperature, bonding load and ultrasonic vibration magnitude is important to the formation of high quality bonds and to the protection of the underlying chip.
It has been observed that wire bonding may cause the bonding pad to lift off or peel back (delaminate) from one or more of the underlying layers, weakening the bonding pad structure and damaging other portions of the chip""s wiring. As shown in FIG. 1, a bonding pad 104 of a conventional bonding pad structure peels or cracks amid a wire bonding process, wherein a substrate 100, a conductive layer 102 which is used as a barrier/glue layer, a passivation layer 106 and a bonding wire 108 are also shown. Such peel back reduces or prevents electrical contact between the bonding pad and the integrated circuit devices on the chip, which decreases the reliability and reduces the life of the chip. The stresses applied during wire bonding processes are much harder to control for chip-on-board assembly methods than for more conventional lead frame packaging technique for a number of reasons. For example, there are far greater variations in the thickness of printed circuit boards than there are in lead frames. Thus, for chip-on-board methods, there are greater variations in the position of the bonding pad with respect to the wire bonding equipment and so an increased likelihood that an appropriate level of force will be applied during wire bonding.
It is desirable to form bonding pad structures exhibiting improved bondability and durability with better adhesion to underlying layers, so that the bonding pad structures are more compatible with conventional packaging techniques.
It is therefore an object of the invention to provide a bonding pad structure having improved bondability and durability.
It is another object of this invention to provide a bonding pad structure which can prevent the bonding pad layer from peeling and cracking amid the wire bonding process.
It is a further object of this invention to provide a bonding pad structure to improve the yield ratio and the quality of electrical connections between integrated circuits on a chip and the printed circuit board.
To achieve these objects, and in accordance with the purpose of the invention, the invention use a bonding pad structure having improved bondability. In one embodiment of this invention, the bonding pad structure comprises a substrate, a first conductive layer on the substrate comprising a plurality of conductive islands, a plurality of conductive plugs on each conductive island, a dielectric layer on the substrate and between the conductive plugs and the conductive islands, and a second conductive layer over the dielectric layer and the conductive plugs.
In another embodiment of this invention, the bonding pad structure has a configuration similar to the one set forth. This bonding pad structure comprises a substrate, a first conductive layer on the substrate comprising a plurality of first conductive islands, a plurality of first conductive plugs on each the first conductive island, a first dielectric layer on the substrate and between the first conductive plugs and the first conductive islands, a second conductive layer over the first dielectric layer and the first conductive plugs comprising a plurality of second conductive islands wherein each the second conductive island is connected to the adjacent first conductive islands by the first conductive plugs, a plurality of second conductive plugs on each the second conductive island, a second dielectric layer on the first dielectric layer and between the second conductive plugs and the second conductive islands, and a third conductive layer over the second dielectric layer and the second conductive plugs. The second conductive island mentioned above can also be arbitrarily connected to the first conductive islands by the first conductive plugs.
In still another embodiment of this invention, the bonding pad structure can be formed by using a dual damascene process, that is, the conductive islands and the conductive plugs are formed together, but other methods should not be excluded. A multilevel dual damascene structure is used to fasten a bonding pad layer to prevent the bonding pad layer from peeling or cracking.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.